1. Field of the Invention
The present invention relates generally to methods for etching silicon layers while employing silicon containing hard mask layers within microelectronics fabrications. More particularly, the present invention relates to methods for etching with smooth sidewall profile silicon layers while employing silicon containing hard mask layers within microelectronics fabrications.
2. Description of the Related Art
As integrated circuit integration levels have increased and integrated circuit device and conductor element dimensions have decreased, it has become increasingly important to form separating adjoining active semiconductor regions of a semiconductor substrate isolation regions which are substantially co-planar with those adjoining active semiconductor regions of the semiconductor substrate. Isolation regions which are substantially co-planar with adjoining active semiconductor regions of a semiconductor substrate are desirable within advanced integrated circuit microelectronics fabrication since such substantially co-planar isolation regions and active semiconductor regions provide a nominally planar surface which optimizes a reduced depth of focus typically encountered within an advanced photoexposure apparatus employed in defining advanced integrated circuit devices and advanced conductor elements of reduced linewidths upon or over those substantially co-planar isolation regions and active semiconductor regions within an advanced integrated circuit microelectronics fabrication.
When forming within an advanced integrated circuit microelectronics fabrication an isolation region substantially co-planar with an adjoining active semiconductor region of a semiconductor substrate, it is common in the art of advanced integrated circuit microelectronics fabrication to employ methods such as shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods when forming the isolation region. Shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods typically provide that a shallow trench is first formed within the semiconductor substrate while employing a composite etch mask layer formed of a patterned silicon nitride layer overlying a patterned pad oxide layer formed upon the semiconductor substrate. The composite etch mask layer is then subsequently employed as an oxidation mask layer when exposed portions of the shallow trench are at least partially thermally oxidized to form at least a thermal silicon oxide trench liner layer within the shallow trench.
While shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are thus desirable within the art of advanced integrated circuit microelectronics fabrication, shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are nonetheless not entirely without problems within advanced integrated circuit microelectronics fabrication. In particular, since it is common in the art of integrated circuit microelectronics fabrication to form upon a semiconductor substrate a composite patterned silicon nitride layer/patterned silicon oxide layer etch mask/oxidation mask layer through a first plasma etch method independent of a second plasma etch method employed in forming a shallow trench within the semiconductor substrate while employing the composite patterned silicon nitride layer/patterned silicon oxide layer as the etch mask layer, there is in general an inefficient use of integrated circuit microelectronics fabrication tooling and materials when forming shallow trenches within semiconductor substrates when employing composite patterned silicon nitride layer/patterned silicon oxide layer etch mask/oxidation mask layers.
In addition, it is also recognized in the art of integrated circuit microelectronics fabrication that sidewall profiles of trenches formed within semiconductor substrates through conventional methods which employ a first plasma etch method in forming a composite patterned silicon nitride layer/patterned silicon oxide layer etch mask layer upon a semiconductor substrate and an independent second plasma etch method in forming a trench within the semiconductor substrate while employing the composite patterned silicon nitride layer/patterned silicon oxide layer as an etch mask layer are often rough.
Inefficient use of integrated circuit microelectronics fabrication tooling and materials is undesirable within advanced integrated circuit microelectronics fabrication since integrated circuit microelectronics fabrication costs are thus increased. Similarly, rough sidewall profiles of shallow trenches formed within semiconductor substrates within integrated circuit microelectronics fabrications are also undesirable since such rough sidewall profiles may impede formation of isolation regions with optimal isolation characteristics within those shallow trenches and thus influence operating parameters of integrated circuit devices formed within adjoining active regions of a semiconductor substrate separated by the shallow trenches.
It is thus desirable in the art of advanced integrated circuit microelectronics fabrication to provide shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods through which there may efficiently, economically and with smooth sidewall profile be formed trenches within silicon semiconductor substrates while employing composite patterned silicon nitride layer/patterned silicon oxide layer etch mask/oxidation mask layers. It is towards that goal that the present invention is most specifically directed.
In a more general sense, it is also towards the goal of efficiently and economically forming an at least partially etched silicon layer within a microelectronics fabrication while employing a patterned silicon containing hard mask layer as an etch mask layer when forming the at least partially etched silicon layer, while simultaneously providing a smooth sidewall profile of the at least partially etched silicon layer, that the present invention is more generally directed.
Methods and materials through which structures such as trenches may be etched within semiconductor substrates are known in the art of integrated circuit microelectronics fabrication.
For example, Goth et al., in U.S. Pat. No. 4,534,826 discloses a method for etching a trench within a semiconductor substrate, where the method employs in addition to a conventional blanket first oxide mask layer and a patterned photoresist layer successively formed upon the semiconductor substrate, a blanket organic polymer layer having formed thereupon a blanket second oxide or nitride layer interposed between the blanket first oxide mask layer and the patterned photoresist layer. Through the method there may be formed through successive patterning of the blanket second oxide or nitride layer, the blanket organic polymer layer and the blanket first oxide layer a trench within the semiconductor substrate, where the trench has substantially perfectly vertical sidewalls.
In addition, Tsang, in U.S. Pat. No. 4,666,555 discloses a plasma etch method for etching a silicon semiconductor material, where the plasma etch method employs a trifluoromethane etchant gas in conjunction with a sulfur hexafluoride etchant gas. By controlling the relative concentration of trifluoromethane etchant gas with respect to the sulfur hexafluoride etchant gas within the plasma etch method a degree of anisotropic character of the plasma etch method may be controlled.
Finally, Drage et al., in U.S. Pat. No. 4,857,138 discloses a plasma etch method for etching a relatively deep trench within a single crystal silicon wafer. The method employs an etchant gas composition comprising fluorotrichloromethane and an inert gas to form the relatively deep trench with at least nearly vertical sidewalls, with improved image transfer and with a rapid etch rate.
Desirable in the art are additional methods and materials through which silicon layers within microelectronics fabrications may be at least partially etched while employing patterned silicon containing hard mask layers, to efficiently and economically provide at least partially etched silicon layers with smooth sidewall profiles. More particularly desirable are methods and materials through which silicon layers and silicon substrates within integrated circuit microelectronics fabrications may be at least partially etched while employing patterned silicon containing hard mask layers to efficiently and economically provide at least partially etched silicon layers or silicon substrates with smooth sidewall profiles. It is towards the foregoing objects that the present invention is directed.